1. Field of the Invention
The present invention relates to an HDTV video decoder and, more particularly, to an HDTV(High Definition TV) video decoder circuit having a 1/4 size frame memory for a progressive scanned or interlace scanned video which is capable of conducting a IDCT(Inverse Discrete Cosine Transform) and motion compensation to fit to the reduced frame memory size.
2. Discussion of the Related Art
The GA(Grand Alliance) HDTV system, which is the U.S.A. HDTV standard, has video compression and multiplexing techniques following the MPEG-2(Moving Picture Experts Group-2) standards. It also has the capability for plural broadcasting video formats including with 24 Hz 30 Hz progressive scanning systems, and a 60 Hz interlaced scanning system for 1920.times.1080 pixels, and 24 Hz, 30 Hz and 60 Hz progressive scanning systems for 1280.times.720 pixels.
A conventional HDTV video decoding device will be explained with reference to the attached drawings.
FIG. 1 illustrates a block diagram of a conventional HDTV video decoder circuit for decoding video data of progressive or interlaced system.
Referring to FIG. 1, the conventional HDTV video decoder circuit includes a VLD(Variable Length Decoder)/demultiplexer 11 for variable length decoding and separating a received HDTV bit stream, an inverse quantizing part 12 for inverse quantizing a coefficient from the VLD/demultiplexer 11 according to a quantizing value, an IDCT part 13 for inverse discrete cosine transformation of the inverse quantized coefficient from the inverse quantizing part 12 to restore the bit stream into a video signal, an adding part 14 for converting the video signal from the IDCT part 13 into to a motion compensated video signal, a frame buffer 15 of 3M byte size for converting the video signal from the adding part into a frame unit video signal, a slice buffer 16 for presenting the video signal from the frame memory 15 in a line unit video signal, a frame buffer 17 of 6 M byte size for converting the video signal from the adding part 14 into a frame unit video signal and storing therein, and a motion compensating part 18 for motion compensation of the video signal from the frame buffer 17 according to an MV(Motion Vector) from the VLD/demultiplexer 11 and applying to the adding part 14.
The operation of the conventional HDTV video decoder circuit will be explained.
Referring to FIG. 1, upon reception of an HDTV bit stream, the VLD/demultiplexer 11 makes a variable length decoding of the bit stream and separates the bit stream into motion information, a quantizing value and at least one coefficient. The separated motion vector is applied to the motion compensating part 18, and the quantizing value and the coefficients are applied to the inverse quantizing part 12. The inverse quantizing part 12 inverse quantizes the coefficient from the VLD/demultiplexer 11 according to the quantizing value, and the inverse quantized coefficient is, restored into a video signal through an inverse DCT of 8.times.8 units in the IDCT part 13, and applied to the adding part 14. The adding part 14 adds the video signal from the IDCT part 13 to a signal predicted in the frame buffer 17 through the motion compensation in the motion compensating part 18 to restore a perfect image which is applies to the frame buffer 15. The frame buffer 15 converts the video signal from the adding part 14 into a frame unit video signal and which is applied to the slice buffer 16, and the slice buffer 16 converts the video signal from the frame buffer 15 into a line unit video signal which is thereafter presented as output. The video signal from the adding part 14 is converted into a frame unit video signal and stored in the frame buffer 17 of 6 M byte size, and the motion compensating part 18 makes a motion compensation of the video signal from the frame buffer 17 according to the motion vector from the VLD/demultiplexer 11 and applies the compensated video signal to the adding part 14.
In addition to the compression application, the DCT also has a video signal decimation application.
A decimated image that is proportional to, for example, a selected region of an N.times.N sized image can be obtained by performing a N.times.N discrete cosine transformation of the N.times.N sized image, selecting a region smaller than N and discarding the rest through a zonal filter, and conducting an inverse discrete cosine transformation suitable to the selected region. In this instant, an image decimated by 1/2 in vertical and horizontal directions can be obtained by using the zonal filter because the resolution of an NTSC image is 1/4 the resolution of an HDTV image.
FIG. 2 illustrates a block diagram of the conventional HDTV video decoder circuit that is decimated by 1/2 in vertical and horizontal directions, and which will be explained herein after, omitting explanations on the identical parts to the parts shown in FIG. 1.
Referring to FIG. 2a the feature of this system is the zonal filter 20 provided between the VLD/demultiplexer 19 and inverse quantizing part 21 of the system shown in FIG. 1, for selecting a quantizing value and a coefficient of a region corresponding to 1/4 of a macro block size among the quantizing values and coefficients from the VLD/demultiplexer 19. The IDCT part 22 in FIG. 2 conducts an inverse discrete cosine transformation of the quantized coefficient from the inverse quantizing part 21 in 4.times.4 pixel units, to restore a video signal. Accordingly, the received HDTV bit stream is finally presented as a video signal decimated by 1/2 in horizontal and vertical directions, i.e., a video signal decimated by 1/4 size.
The operation of the system shown in FIG. 2 will be explained with reference to FIGS. 3.about.5 in detail. FIG. 3 illustrates an operational state of the zonal filter shown in FIG. 2, and FIG. 4 illustrates an array of pixels for explaining an interpolation of 1/4 PEL resolution level using a motion vector.
A received HDTV bit stream is subjected to variable length decoding in the VLD/demultiplexer 19, from which motion vectors are applied to the motion compensating part 27, and quantizing values and coefficients are applied to the zonal filter 20. The received quantizing values and coefficients are filtered in the zonal filter 20; of the received quantizing values and coefficients, the quantizing values and coefficients in a region corresponding to a 4.times.4 pixel size are selected as shown in FIG. 3. Therefore, the zonal filter 20 has a macro block buffer corresponding to the 4.times.4 pixel size. That is, as shown in FIG. 3, the zonal filter 20 selects coefficients only from the 4 .times.4 region of the coefficients received from the VI.D/demultiplexer 19 and applies to the inverse quantizing part 21. Accordingly, a production rate of the inverse quantizing part 21 is reduced to 1/4 and an IDCT unit of the IDCT part 22 is also changed to 4.times.4. Thus, the coefficients from the zonal filter 20 are inverse quantized in the inverse quantizing part 21 according to a quantizing value, and the quantized coefficients from the quantizing part 21 is inverse discrete cosine transformed in the IDCT part 22, to be restored as a perfect video signal.
In this time, since the IDCT unit is changed to 4.times.4 unit, the function of the IDCT part 22 should also be changed as follows, ##EQU1##
Therefore, the number of operations required the 4.times.4 IDCT part 22 implementation is reduced by a factor of approximately 1/16. And, a capacity of the frame memory required for the motion compensating part 27 and the frame buffer 26 is also reduced by a factor of 1/4. Accordingly, a volume of hardware required for implementation of such a video decoder is reduced to about below 1/4 in overall.
In the meantime, the video signal from the IDCT part 22 is added in the adding part 23 to the video signal motion compensated in the motion compensating part 27, and the video signal from the adding part 23 is, converted into a frame unit video signal in the frame buffer 24 and into a line unit video signal in the slice buffer 25, and finally presented. The video signal from the adding part 23 is stored in the frame buffer 26 in frame units for motion compensation; it is then applied to the motion compensating part 27. In this case, in the MPEG-2 video compression standard, a half-pet resolution level is applied to the interpolation in the motion compensation for improving correlation. That is, a motion vector transmitted through a channel is of the half-pel resolution. Accordingly, when of implementing a decoder in which the zonal filter 20 only selects a 4.times.4 region of 8.times.8 blocks to produce an image decimated by 1/2 in horizontal and vertical directions respectively, a motion compensation of an interpolation to a quarter pel resolution in horizontal and vertical directions respectively are applied based on the received half-pel resolution motion vector for substantially reducing errors occurred in the motion compensation, which has been verified through a mock test. FIGS. 4 and 5 illustrate examples of such interpolation techniques for motion compensation. That is, of received horizontal and vertical 6 bit motion information, each of 2 least significant bits contains information which can interpolate up to 1/4 pel resolution, and specific interpolating methods using the information are shown in FIGS. 4 and 5.
However, though the conventional HDTV video decoder can effectively decode a bit stream of a progressive scanned image compressed according to the MPEG-2 standard, and having a frame that is composed of pixels formed at the same time, the conventional HDTV video decoder experiences severe errors when decoding an interlace scanned image having a frame that is composed of two fields of different time bases. That is, though there is no problem in decoding a progressive scanned image or interlace scanned image into a field picture if a vertical direction decimation is conducted applying a vertical direction 1/2 zonal filtering and a 4.times.4 IDCT, in case the picture quality suffers from vital damage because of loss of time information when decoding mixed images of two times bases within a frame, like the case of decoding an interlace scanned image into a frame picture. As this vertical decimation is not practicable, an 8.times.4 IDCT and a frame memory reduced by 1/2 in a horizontal direction are used, which results in increased costs.